This application is based upon and claims priority of Japanese Patent Application No. 2002-251953, filed on Aug. 29, 2002, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device manufacturing method and, more particularly, a method of manufacturing a nonvolatile semiconductor memory using ferroelectric material as a capacitor dielectric film (FeRAM: Ferroelectric Random Access Memory).
2. Description of the Prior Art
After the memory chip of FeRAM has been manufactured, the monitor test and the device test are carried out in order to decide whether or not the chip can be delivered.
FIG. 1 is a flowchart showing FeRAM manufacturing steps containing these tests.
The FeRAM chip is completed by executing sequentially the CMOS process of forming the control MOS transistor, the ferroelectric process of forming the ferroelectric capacitor over the control MOS transistor, and the wiring process of forming the wirings over the capacitor. Then, the monitor test as the first delivery decision test and the device test as the second delivery decision test are executed successively in the wafer state. Then, if the chip is decided as the defective in the monitor test or the device test, the wafer having the chip is dumped or the manufacture is started over again from the first CMOS process.
The monitor test is performed by using the cell test pattern connecting circuit elements each having the same structure as the main chip in parallel, and measuring transistor characteristics, contact resistance, wiring resistance, inter-wiring leakage, ferroelectric capacitor characteristics, etc. Such chip is defined as the non-defective if these measured values are within the criteria, but such chip is defined as the defective if these measured values are out of the criteria.
The ferroelectric capacitor characteristics out of the above measurement items are the ferroelectric capacitor characteristics such as an amount of residual dielectric polarization (QSW), an amount of effective residual dielectric polarization (Qeff), saturation voltage (V90), capacitor leakage current (Lcap), capacitor capacitance (Ccap), and the like. These measurement items are measured by using the cell test pattern as set forth in Patent Application Publication (KOKAI) Hei 11-176195. These measurement items are particularly effective to evaluate the results such as crystallinity and composition of the ferroelectric substance, etc.
The device test is composed of the direct current test for measuring operation states of the input protection circuit, the alternating current test for measuring operation states of peripheral circuits and all the cells, and the retention test for checking whether or not data of the ferroelectric capacitor can be held. Test results are evaluated in accordance with predetermined criteria to define whether or not the chip is the non-defective or the defective.
Meanwhile, in FeRAM, particularly the ferroelectric capacitor characteristics are important and also yield of the retention test is important because FeRAM is the nonvolatile memory. The ferroelectric capacitor forming step is the most important process to affect the ferroelectric capacitor characteristics and the retention performance (data retention capability).
However, even if any trouble is present in the ferroelectric capacitor forming step, the FeRAM must be completed by executing the manufacturing steps up to the final step, in order to make the above delivery decision in the prior art. Therefore, if the device is defined as the defective according to the result of test, reduction in yield is brought about and also man-hours needed for executing the manufacturing steps are totally wasted, so that throughput is lowered. Under such circumstances, it is desired that, if there is any trouble in the intermediate steps, the delivery decision should be made in the early stage without executing the steps until the final manufacturing step.
It is an object of the present invention to provide a semiconductor memory device manufacturing method capable of achieving improvement of yield and improvement of throughput by feeding back trouble to the manufacturing steps in its early stage if such trouble is caused in the middle of manufacturing steps.
A semiconductor memory device manufacturing method of the present invention, in the method of manufacturing a semiconductor memory device provided with a capacitor over the semiconductor substrate, which has a laminated structure of a lower electrode made of a first conductive film, a capacitor dielectric film made of a dielectric film, and an upper electrode made of a second conductive film, is characterized in comprising the steps of forming an insulating film over the semiconductor substrate; forming a capacitor on the insulating film; forming a dielectric monitor, which is made of same material and has a same layer structure as the capacitor, on the insulating film; measuring characteristics of the dielectric monitor in middle of a process of forming the capacitor; and evaluating the capacitor based on measured results of the characteristics of the dielectric monitor.
Meanwhile, in the situation that, when process failure is caused in forming the capacitor, an amount of residual dielectric polarization does not satisfy the criterion, it is desired to decide immediately in the relevant step whether or not the in-process wafer should be abandoned or such wafer should be reproduced. However, in the prior art, the delivery decision is made by the monitor test or the device test after all manufacturing steps have been completed. Therefore, if the wafer is reproduced, the reproducing operation becomes complicated to bring about reduction in the yield. Also, wasteful man-hours are consumed in the subsequent manufacturing steps after the relevant step in which the trouble is generated, and thus reduction in throughput is brought about.
The present invention comprises the step of forming the dielectric monitor in addition to the step of forming the capacitor. And it further comprises the step of measuring the characteristics of the dielectric monitor in the middle of the process of forming the capacitor, and the step of evaluating the capacitor based on measured results of the characteristics of the dielectric monitor.
Since the characteristics of the dielectric monitor are measured in the middle of the process of forming the capacitor, the abnormality of crystallinity, composition, etc. of the dielectric film can be detected via the measured value of the capacitor characteristics such as the amount of residual dielectric polarization (QSW), etc. Therefore, before completion of the formation of the capacitor, the evaluation of the capacitor can be made to decide in the early stage whether or not the capacitor forming step should be continued, or the concerned wafer should be abandoned, or the step should go back to the step of reproducing the capacitor. Even if the failure is caused in the capacitor forming process, the evaluation can lead to elimination of wasteful man-hours in the subsequent manufacturing steps after the relevant step in which the failure is caused, and thus improvement in throughput can be achieved. In addition, if the reproduction is selected, merely the defective manufacturing step is required as the reproducing operation, and thus the reproducing operation can be simplified and also improvement in yield can be achieved.
Also, the yield of the retention characteristics of the capacitor, etc. can be predicted via the measured values of the capacitor characteristics such as an amount of residual dielectric polarization (QSW), etc. Therefore, only the in-process wafers with high yield can be shifted selectively to later steps, and thus improvement in the device yield can be achieved.